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Openrisc

First CVE: Apr 18, 2023Active for: 3 yearsTotal CVEs: 5

Openrisc is an open-source processor architecture project whose vulnerability footprint centers on processor core implementations and firmware, particularly the MOR1KX and OR1200 designs. The durable signal across its disclosures reflects authentication and default-permission issues in embedded firmware contexts, alongside cases where vulnerability details remain limited; live severity, exploitation, and exposure counts are shown alongside this summary.

FAUCET AI Generated
5
Total CVEs
More Total CVEs than 83% of tracked vendors
1.3
Avg CVEs / Product / Year
More Avg CVEs / Product / Year than 74% of tracked vendors
8.1
Avg CVSS Score
Higher Avg CVSS Score than 78% of tracked vendors
0.0%
In CISA KEV
Bottom 1%

Trends Over Time

The number and severity of CVEs published that impact products developed by Openrisc over time

Volume of CVEsAvg CVSS Base Score
First CVE
Apr 18, 2023
3 years ago
Most Recent CVE
Apr 18, 2023
1,193 days ago

Products(4 total)

Top CVEs

Signals from CVEs in this vendor scope (5 CVEs).

5 CVEs · Highest risk first

CVEPublishedCVSSRiskKEVExploit
CVE-2021-40507CRITICAL
An issue was discovered in the ALU unit of the OR1200 (aka OpenRISC 1200) processor 2011-09-10 through 2015-11-11. The overflow flag is not being updated correctly for the subtract
Apr 18, 20239.830NONO
CVE-2021-40506CRITICAL
An issue was discovered in the ALU unit of the OR1200 (aka OpenRISC 1200) processor 2011-09-10 through 2015-11-11. The overflow flag is not being updated for the msb and mac instru
Apr 18, 20239.830NONO
CVE-2021-41612HIGH
An issue was discovered in the ALU unit of the OpenRISC mor1kx processor. The carry flag is not being updated correctly for the subtract instruction, which results in an incorrect
Apr 18, 20238.828NONO
CVE-2021-41614HIGH
An issue was discovered in the controller unit of the OpenRISC mor1kx processor. The read/write access permissions to the Exception Program Counter Register (EPCR) are not implemen
Apr 18, 20237.824NONO
CVE-2021-41613MEDIUM
An issue was discovered in the controller unit of the OpenRISC mor1kx processor. The write logic of Exception Effective Address Register (EEAR) is not implemented correctly. User p
Apr 18, 20234.318NONO
View all 5 CVEs →

CVE Severity & Scoring

Severity distribution of CVEs that affect this vendor's products5 CVEs
20%
40%
40%
Severity distribution among all CVEs352,231 CVEs
45%
40%
11%
MediumHighCritical
Attack Vector
Local1 (20.0%)
Network4 (80.0%)
Unknown0 (0.0%)
Physical0 (0.0%)
Adjacent Network0 (0.0%)
Attack Complexity
Low5 (100.0%)
High0 (0.0%)
Unknown0 (0.0%)
User Interaction
None5 (100.0%)
Unknown0 (0.0%)
Required0 (0.0%)
Privileges Required
Low3 (60.0%)
High0 (0.0%)
None2 (40.0%)
Unknown0 (0.0%)

Exploit Exposure

Signals from CVEs in this vendor scope (5 CVEs).

CISA KEV
0 CVEs
0.0% of CVEs· Bottom 1%
Metasploit
0 CVEs
0.0% of CVEs· Bottom 1%
Nuclei
0 CVEs
0.0% of CVEs· Bottom 1%
ExploitDB
0 CVEs
0.0% of CVEs· Bottom 1%

Social Chatter

An overview of all social media posts that mention a CVE ID that affects a product developed by Openrisc.

Media Mentions

Media articles that mention a CVE ID that affects a product developed by Openrisc — matched by CVE ID, not by vendor name.

Top CNAs Publishing CVEs For Openrisc's Products

View all 1 CNAs →

Top CWEs