Max 10 Fpga

Vendor:

First CVE: Mar 12, 2020 · Active for 6 years

1
Total CVEs
Bottom 1%
1.0
Avg CVEs / Year
Bottom 1%
5.9
Avg CVSS
Higher Avg CVSS than 18% of tracked products
0.0%
KEV Rate
Bottom 1%

Trends Over Time

The number and severity of CVEs published that impact Max 10 Fpga over time

Volume of CVEsAvg CVSS Base Score
First CVE
Mar 12, 2020
6 years ago
Most Recent CVE
Mar 12, 2020
2,327 days ago

CVE Severity & Scoring

Max 10 Fpga1 CVEs
All CVEs352,719 CVEs
Medium
Attack Vector
Local0 (0.0%)
Network0 (0.0%)
Unknown0 (0.0%)
Physical1 (100.0%)
Adjacent Network0 (0.0%)
Attack Complexity
Low1 (100.0%)
High0 (0.0%)
Unknown0 (0.0%)
User Interaction
None1 (100.0%)
Unknown0 (0.0%)
Required0 (0.0%)
Privileges Required
Low1 (100.0%)
High0 (0.0%)
None0 (0.0%)
Unknown0 (0.0%)

Top CVEs

Signals from CVEs in this product scope (1 CVEs).

1 CVEs · Highest risk first

CVEPublishedCVSSRiskKEVExploit
Improper configuration in block design for Intel(R) MAX(R) 10 FPGA all versions may allow an authenticated user to potentially enable escalation of privilege and information disclo
Mar 12, 20205.916NONO

Exploit Exposure

Signals from CVEs in this product scope (1 CVEs).

CISA KEV
0 CVEs
0.0% of CVEs· Bottom 1%
Metasploit
0 CVEs
0.0% of CVEs· Bottom 1%
Nuclei
0 CVEs
0.0% of CVEs· Bottom 1%
ExploitDB
0 CVEs
0.0% of CVEs· Bottom 1%

Social Chatter

Signals from CVEs in this product scope (1 CVEs).

Media Mentions

Signals from CVEs in this product scope (1 CVEs).

Top CNAs Publishing CVEs For Max 10 Fpga

Versions

No cataloged versions.